Present and planned semiconductor processes are providing devices for integrated circuits having process minimum feature sizes of 100 nanometers and smaller. Transistors fabricated in these advanced semiconductor process nodes (usually referred to as “sub-100 nm” nodes) are subject to large variability in the threshold voltages (Vth), even in local areas on the device. As a result, the transistors used to fabricate an SRAM cell, for example, may exhibit a large variability in the threshold voltage Vth. The variability in the threshold voltages has a negative impact on the reliability and performance of the SRAM cell, and this directly affects the operating margins of the cell, such as static noise margin (SNM). In order to maintain the desired production yields required for cost effect manufacture of integrated circuits incorporating the SRAM arrays formed using these SRAM cells, the operating margins must be expanded to compensate for the variable thresholds in the transistor circuits. If this is not done, then many IC devices will fail post manufacture reliability tests, thus the manufacturing yield will fall, and the cost of each integrated circuit that does pass the tests will rise commensurately.
Highly integrated semiconductor circuits are increasingly important, particularly in the field of producing battery operated devices such as cell phones, portable computers such as laptops, notebook and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web-browsers and the like, and these integrated circuits increasingly include on-board data storage. As is known in the art, such storage may take the form of static memory or SRAMs in which arrays of multiple transistor cells are provided, each cell may have for example six transistors to form a “6T” cell, in a well known alternative, a dual ported SRAM circuit may be provided using eight transistors per cell, that is, an “8T” cell may be used. Also, as is known in the memory art, if the individual memory cells are arranged to provide a small voltage output when read, that small voltage can be sensed and amplified by a differential sense amplifier, the area required for each cell may be kept small, and the speed of operation can be increased. Because the sense amplifiers can be shared across many cells, the use of the sense amplifiers does not add significant area to the layout of the memory array.
Static memory offers excellent storage in that no refresh circuitry is required, so long as there is power applied to the SRAM array, the data stored in the cells will be maintained. Dynamic memory or DRAM offers excellent density and required minimum silicon area, and is often provided as fast access memory for a processor, such as a first level cache memory or scratchpad memory. In the prior art it is known to produce both SRAM arrays and DRAM arrays as stand alone integrated circuits using dedicated semiconductor process techniques that are specifically optimized to produce space and power efficient DRAM devices. Sometimes a battery backed up SRAM is used as an alternative to more permanent storage such as non-volatile memory, e.g. FLASH or EEPROM memory. The battery maintains the data in the cells when the system is not supplying power to the memory to create “non-volatile” memory for long periods of time.
As semiconductor process technology advances have continued, recent fabrication technology has enabled the SRAM and DRAM arrays to be incorporated into large, highly integrated ICs, sometimes called “SOCs” or “systems on a chip.” Typical applications for these embedded SRAMS include for use as register files, FIFOs, stacks and the like, and for fast memory adjacent a processor or controller core such as cache memory, as fast scratchpad memory, or to reduce the need for, or totally replace, discrete DRAM devices in systems where space is at a premium.
In conjunction with the increasing use of RAMs embedded with various other logic circuitry on a single integrated circuit, process technologies for manufacturing of integrated circuits continue to shrink. As the scaling of the dimensions of CMOS integrated circuitry gets smaller, certain dominant problematic effects become increasingly dominant. At the sub 100 nanometer manufacturing nodes, one such effect is that the threshold voltages for the transistors are highly variable. This effect must be compensated for to maintain reliable operation of the circuits.
FIG. 1 depicts a typical prior art 6T SRAM cell 11. 6T and 8T SRAM cells are described, for example, in U.S. Pat. Nos. 6,417,032 and 6,569,723, which are co-owned by the assignee of the present application and each of which is hereby incorporated by reference. In FIG. 1, access pass gate transistors PG1, PG2 are coupled to the word line WL and when the word line is active (high for an NMOS pass gate, low for a PMOS pass gate as is known in the art), the column or bit lines BL and BLZ are coupled to the simple cross coupled cell latch formed from two CMOS inverter pairs of pull up transistor PU1, pull down transistor PD1, and pull up transistor PU2, and pull down transistor PD2. The two inverters are cross-coupled to form a latch. As is known in the art, the latch will be overdriven for a write cycle by complementary data on the bit line pair, and that data will replace whatever data was previously stored in the cross coupled latch. In contrast, for a read cycle when no voltage is initially present on the bit lines BL and BLZ, and so the voltages at latch nodes I1, I2 will be output through the pass gates to provide read data for the bit lines. The bit lines BL and BLZ are differential, which is, the data on bit line BL during a read or write cycle will be the opposite of the data on bit line BLZ.
The use of complementary differential level bit lines as the data lines for the SRAM array enables the use of sense amplifiers. Sense amplifiers can sense a small, differential voltage difference presented on complementary column, or bit, lines and amplify the sensed differential voltage to a full logic level voltage. In this way the signals are made available as logic level signals for use as data by the remainder of the integrated circuit or system. Because the sense amplifier can be coupled to many storage cells, the area required for the sense amplifier transistors is not a disadvantage. Because the signals output by any particular cell in the memory array need not reach a full “logic” level, the speed of the cells can be increased for read and write cycles, as is well known in the art.
FIG. 2 depicts in a plan view a block diagram of a memory array of the prior art using SRAM cells 11 such as the one illustrated in FIG. 1 arranged in columns and rows, with a sense amplifier 13 coupled to a group of cells in a column. In FIG. 2, a plurality of SRAM cells 11 labeled “SRAM Cell” are coupled to a sense amplifier 13. Each SRAM cell 11 stores a bit of data and each are coupled to a word line. There is a word line driver for each row of the SRAM array and these are shown as WL0-WLN, with the replicator dots indicating there are many rows in the array. The columns are also replicated across the array, generally there is a column for each bit in a data word associated with the array, further it is known in the prior art to have millions of cells grouped into subarrays that are active during a cycle depending on a row and column address decode from control logic. Sense amplifiers 13 may be provided for each column in an array or subarray, preferably for larger arrays the sense amplifiers 13 are coupled to bit lines through multiplexers and de-multiplexers to share the sense amplifiers 13 and so minimize the silicon area required to implement the SRAM array.
FIG. 3 depicts an SRAM array comprised of subarrays 35 each having a plurality of memory cells 11 inside (not visible in the portion depicted). The memory cells are arranged as columns of cells, with each column being associated with one bit of a data word, the I/O buffers 39 couple the data lines (not shown) which run in a columnar direction, to a data bus. Wordline decoders 33 activate the particular word line associated with a row of the memory cells 11 within the subarrays 35, responsive to an address value received from outside the array. Each subarray of cells is coupled to a sense amplifier 37, which receives two data lines, usually called bit line or BL and a complementary bit line or BLZ. Control logic 41 provides the various signals to the sense amplifiers 37 and the I/O buffers 39 to cause the data presented at the I/O ports to be written to the appropriate row of memory cells, or, to cause stored data to be read from the appropriate row of memory cells so as to output data from the I/O buffers 39. All of these operations, and the circuits required, are well known in the art.
The use of improved semiconductor processing makes embedding RAM memory of both dynamic and static types along with other functional blocks more attractive in ASIC or semi-custom IC manufacture. Improved isolation and buried layer techniques, coupled with advanced photolithographic techniques, make it possible to provide the smaller transistor sizes and capacitors required for implementing a DRAM block in one portion of an integrated circuit, an SRAM block in another portion, while still processing a different portion of the integrated circuit to produce the larger transistors, and even analog components such as resistors, required for other applications, in a single piece of silicon. These advances make efficient and compact DRAM arrays even more important. FIG. 4 depicts a typical highly integrated circuit, ASIC or microprocessor of the prior art labeled IC1, having an I/O buffer portion, an embedded DRAM block A, an embedded SRAM block B, an external memory interface (sometimes called an “EMIF” block) a microprocessor core (which may include, inter alia, DSP, CPU, RISC, ARM and other types of microprocessor, microcontroller or programmable machine cores) and some user defined logic provided to make the integrated circuit particularly useful for a given purpose, perhaps analog to digital converters, sensors, image buffers, or the like.
In the SRAM art, it is known to vary the operating voltages supplied to the SRAM memory cells to attempt to improve the noise margins such as the static noise margins, for example. Providing a variable supply voltage depending on which portion of the operation cycle is being performed is one known prior art approach, however this approach requires a complex supply voltage line and extra control circuitry. A paper entitled “A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Stabilizing Circuits,” to Ohbayahsi et al., published in the Digest of Technical Papers, 2006 Symposium on VLSI Circuits, IEEE (2006), proposes additional read access circuitry in the form of dummy or replica access transistors called “RATs” that match the access transistors in the cells. These normally “on” transistors lower or suppress the word line voltages supplied to the SRAM cells to improve the read noise margins. Another paper, entitled “Wordline and Bitline Pulsing Schemes for improving SRAM Cell Stability in low-Vcc 65 nm CMOS Design,” to Khellah et al., published in the Digest of Technical Papers, 2006 Symposium on VLSI Circuits, IEEE (2006), also discloses added circuitry to address the SRAM operating stability. In this approach, a short pulse is used on the active word lines. While this short pulse on the word lines has a positive impact on the read cycle operating margins, the paper also describes that this approach actually has a negative impact for sense amplifier margins and for the write margins. The recommended approach disclosed in the paper adds a “write back” cycle to the read cycle. In the implementation provided by the paper to Khellah et al. the word line is pulsed twice for each cycle. This two pulse word line approach requires additional control circuitry complexity; power consumption is increased, and because the write back for each cycle means that each column requires its own dedicated sense amplifier, area is also greatly increased over more space efficient shared sense amplifier approaches.
The Khellah et al. paper also studied the impact of the bit line voltage on margins and found that if the bit line voltage were reduced slightly, the expected failure rate greatly improved. Khellah et al. proposes a circuit to lower the bit lines during a read operation just before the word lines are activated.
The SRAM prior art therefore provides a word line maintained at a single voltage during access cycles, and the noise margin problems of the cells are addressed inefficiently by the prior art. A need thus exists for an improved approach to increasing the static noise margins for SRAM cells implemented with transistors fabricated at the present semiconductor process nodes, including some compensation for the problems associated with the large variability in the transistor threshold voltages, without increases in circuit area or power consumption.